Logic Synthesis and Verification Algorithms - Gary D. Hachtel - Books - Springer - 9780792397465 - June 30, 1996
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Gary D. Hachtel
Logic Synthesis and Verification Algorithms 1996 edition

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Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

564 pages, biography

Media Books     Hardcover Book   (Book with hard spine and cover)
Released June 30, 1996
ISBN13 9780792397465
Publishers Springer
Pages 564
Dimensions 178 × 254 × 35 mm   ·   1.41 kg
Language English  

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