Logic Synthesis and Verification Algorithms - Gary D. Hachtel - Books - Springer-Verlag New York Inc. - 9781475770360 - March 18, 2013
In case cover and title do not match, the title is correct

Gary D. Hachtel
Logic Synthesis and Verification Algorithms Softcover reprint of the original 1st ed. 1996 edition

Price
HK$ 704
excl. VAT

Ordered from remote warehouse

Expected to be ready for shipping Jun 17 - 23

Our customers say:

14-day return policy in accordance with European consumer protection law
Top ranking on Trustpilot
Add to your iMusic wish list

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

596 pages, biography

Media Books     Paperback Book   (Book with soft cover and glued back)
Released March 18, 2013
ISBN13 9781475770360
Publishers Springer-Verlag New York Inc.
Pages 564
Dimensions 178 × 254 × 31 mm   ·   1.03 kg
Language English  

Mere med samme udgiver

See all of Gary D. Hachtel ( e.g. Paperback Book and Hardcover Book )