Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers: Modeling, Simulation, Analysis, and Design Methodologies - Analog Circuits and Signal Processing - Xu Wang - Books - Springer Nature Switzerland AG - 9783032271853 - September 2, 2026
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Xu Wang
Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers: Modeling, Simulation, Analysis, and Design Methodologies - Analog Circuits and Signal Processing

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Expected delivery Sep 10 - 15
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This book presents a rigorous and practically grounded treatment of jitter and spur minimization in fractional-N digital phase locked loops (DPLLs), addressing one of the most critical challenges in modern frequency synthesis.

Media Books     Hardcover Book   (Book with hard spine and cover)
To be released September 2, 2026
ISBN13 9783032271853
Publishers Springer Nature Switzerland AG
Pages 246
Dimensions 150 × 220 × 20 mm   ·   525 g   (Weight (estimated))

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