Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing - Katarzyna Radecka - Books - Springer-Verlag New York Inc. - 9781402076527 - November 30, 2003
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Katarzyna Radecka
Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing 2003 edition

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216 pages, biography

Media Books     Hardcover Book   (Book with hard spine and cover)
Released November 30, 2003
ISBN13 9781402076527
Publishers Springer-Verlag New York Inc.
Pages 216
Dimensions 155 × 235 × 14 mm   ·   548 g
Language English  

See all of Katarzyna Radecka ( e.g. Paperback Book and Hardcover Book )